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FPGA-Based Model of a 3-Phase Induction Motor using VHDL

Real-time motor dynamics modeled in hardware, reducing HIL time & cost by 40%+ and enabling rapid control validation for EV powertrains.

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Project Summary

Objective

Develop a synthesizable VHDL model of a 3-phase induction motor that accurately replicates electromagnetic and mechanical dynamics in real-time, enabling controller-in-the-loop and hardware-in-the-loop testing without reliance on physical prototypes.

Use Cases

  • EV inverter control validation (FOC, V/Hz, DTC).
  • Rapid HIL prototyping & design iteration.
  • Teaching & research (power electronics, drives).
  • Safety testing without high-power hardware.

Methodology

Discretized state-space motor equations (stator/rotor flux linkages, dq-axis model), implemented fixed-point arithmetic in VHDL, and orchestrated compute with a Moore FSM. Verified against MATLAB/Simulink golden models and timing-closed on FPGA.

Results

  • >40% reduction in HIL test time & cost.
  • Stable real-time update @ clock-gated 50–100 MHz.
  • Torque ripple & THD trends matched Simulink within tolerance.
  • Deterministic latency for control-loop evaluation.

Future Work

Integrate PMSM model variants, parameter self-identification, thermal derating, and AXI-based co-simulation to accelerate closed-loop algorithm research (MPC, disturbance observers).

Key Contributions

  • VHDL motor core + Moore FSM for robust timing.
  • Fixed-point strategy with saturation & scaling guards.
  • Reusable testbench & metrics (overshoot, settling, THD).
  • Clean interface for inverters & control IP blocks.

Figures & Visuals

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Three-Phase Waveforms
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RTL Schematic of Motor
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Rotor Current
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Power analysis of Rotor

Implementation Details

Numerical Core

dq-axis state update with trapezoidal discretization; clamped accumulators to prevent overflow; configurable timestep for stability margins in closed loop.

Control Interface

Clean ports for inverter & control IP (FOC/PI); strobe-ready handshake; optional AXI-lite for parameter tuning and data read-out.

Verification

Testbench drives multi-scenario sweeps: load steps, voltage sags, and frequency ramps; reports overshoot, settling, RMS error, and THD.